This application claims priority to Korean Patent Application No. 2004-32501, filed on May 8, 2004, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates generally to PRAM (phase-change random access memory) devices, and more particularly, to controlling the width of a set/reset pulse in a PRAM device in response to a peripheral temperature of the PRAM device.
2. Description of the Related Art
A PRAM (phase-change random access memory) device is a non-volatile memory which stores data using materials such as Ge—Sb—Te alloys with resistance that changes with temperature. Such a phase change material, used in a cell of the PRAM, melts or crystallizes when heated depending on temperature and heating time to store information. Changing the phase of the phase change material requires a high temperature, above 900° C., typically obtained by Joule heating from current flowing through the phase change material.
Data is written by flowing current through the phase change material for Joule heating. When the phase change material is heated above its melting temperature to thereafter be quickly cooled, the phase change material becomes amorphous (i.e., in a ‘reset’ state) to store a data bit of ‘1’. Alternatively, when the phase change material is heated above its crystallization temperature and maintained at that temperature for a predetermined time before cooling, the phase change material becomes crystalline (i.e., in a ‘set’ state) to store a data bit of ‘0’.
Data is read from a PRAM cell by selecting a bit line and a word line for that PRAM cell, flowing a current through that PRAM cell, and distinguishing ‘1’ from ‘0’ from the voltage generated from the variable resistance of the phase change material of that PRAM cell.
The write operation for a PRAM cell depends greatly on the change of peripheral temperature. Peripheral temperature is a temperature of the semiconductor substrate having the PRAM cell fabricated therein. Such peripheral temperature determines a write current and a dynamic resistance of the phase change material of the PRAM cell.
Generally, with increased peripheral temperature, the drive performance of transistor(s) generating the write current deteriorates resulting in decreased write current and in decreased dynamic resistance of the phase change material. Accordingly, the heat energy (i.e., temperature) from Joule heating is greatly reduced such that the phase change material may be incompletely crystallized or melted. As a result, the difference in resistance between a reset state and a set state is diminished, possibly causing read errors.
FIG. 1 shows a graph of reset resistance (R_RESET) and set resistance (R_SET) versus peripheral temperature. Referring to FIG. 1, the ratio of R_RESET to R_SET decreases significantly with increased peripheral temperature because the phase change material may not reach the crystallization or melting temperatures at the higher peripheral temperature. As a result, the sensing margin for distinguishing a set state from a reset state during a data read operation is reduced at the higher peripheral temperature.
FIG. 2A shows a graph of reset write current (I_RESET) and set write current (I_SET), versus peripheral temperature. FIG. 2B shows a graph of reset heat energy (E_RESET) and set heat energy (E_SET), versus peripheral temperature. Referring to FIG. 2A, with higher peripheral temperature, the performance of drive transistor(s) deteriorates for reduced write current (I_RESET and I_SET).
Referring to FIG. 2B, heat energy (E_RESET and E_SET) is generated from Joule heating which is proportional to the square of the current flowing through the PRAM cell and to the resistance of the phase change material. With increased peripheral temperature, the current flowing through the PRAM cell and the resistance of the phase change material are reduced such that the heat energy is quickly reduced. As a result, the phase change material is incompletely crystallized or melted, with decreased difference between the reset resistance and the set resistance causing sensing error during a read operation.
Also with increased peripheral temperature, the performance of drive transistor(s) deteriorates, and the pulse widths of a set pulse and a reset pulse become longer. The pulse width of a set/reset pulse determines a set/reset current for setting the phase change material in a set/reset state. The longer pulse width of a set pulse increases the resistance of the phase change material in the set state, further reducing the difference between the reset and set resistances and increasing current consumption of the PRAM device.